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HT82V26A
16-Bit CCD/CIS Analog Signal Processor
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: 5V (Typ.) * Low power consumption at 400mW (Typ.) * Power-down mode: Under 2mA (Typ.) * 16-bit 30 MSPS A/D converter * Guaranteed wont miss codes * 1~6 programmable gain * Correlated Double Sampling * 250mV programmable offset * Input clamp circuitry * Internal voltage reference * Multiplexed byte-wide output (8+8 format) * Programmable 3-wire serial interface * 3V/5V digital I/O compatibility * 3-channel operation up to 30 MSPS * 2-channel (Even-Odd) operation up to 30 MSPS * 1-channel operation up to 25 MSPS * 28-pin SSOP/SOP package (lead-free on request)
Applications
Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals
General Description
The HT82V26A is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of tri-linear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), and a high performance 16-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset and operating mode adjustments. The HT82V26A operates from a single 5V power supply, typically consumes 400mW of power.
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HT82V26A
Block Diagram
AVDD AVSS REFT REFB AVDD AVSS DRVDD DRVSS
V IN R
CDS
+ 9 - B it DAC
PGA BANDGAP R e fe re n c e PGA 3 .1 MUX 1 6 - B it ADC C o n fig u r a tio n R e g is te r MUX R e g is te r 6 RED GREEN BLUE D ig ita l C o n tro l In te rfa c e 16 1 6 :8 MUX 8
OE
V IN G
CDS
+ 9 - B it DAC
DOUT
V IN B
CDS
+ 9 - B it DAC 9
PGA
OFFSET
In p u t C la m p B ia s
G a in R e g is te r s
SC LK SLO AD SDATA
RED GREEN BLUE
O ffs e t R e g is te r s AD CCLK
CDSCLK1
CDSCLK2
Pin Assignment
CDSCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
H T82V26A 2 8 S S O P -A /S O P -A
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HT82V26A
Pin Description
Pin No. 1 2 3 4 5 6 7~14 15 16 17 19, 27 18, 28 20 21 22 23 24 25 26 Pin Name CDSCLK1 CDSCLK2 ADCCLK OE DRVDD DRVSS D7~D0 SDATA SCLK SLOAD AVSS AVDD REFB REFT VINB CML VING OFFSET VINR I/O DI DI DI DI P P DO DI/DO DI DI P P AO AO AI AO AI AO AI Description CDS reference clock pulse input CDS data clock pulse input A/D sample clock input for 3-channels mode Output enable, active low Digital driver power Digital driver ground Digital data output Serial data input/output Clock input for serial interface Serial interface load pulse Analog ground Analog supply Reference decoupling Reference decoupling Analog input, blue Internal reference output Analog input, green Clamp bias level decoupling Analog input, red
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Logic Inputs VIH High Level Input Voltage (CDSCLK1, CDSCLK2, ADCCLK, OE, SCK, SLOAD) Low Level Input Voltage (CDSCLK1, CDSCLK2, ADCCLK, OE, SCK, SLOAD) High Level Input Voltage (SDATA) Low Level Input Voltage (SDATA) High Level Input Current Low Level Input Current Input Capacitance 3/4 3/4 2 3/4 3/4 V Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
VIL VIH1 VIL1 IIH IIL CIN Rev. 1.00
3/4 3/4 3/4 3/4 3/4 3/4 3
3/4 3/4 3/4 3/4 3/4 3/4
3/4 2.5 3/4 3/4 3/4 3/4
3/4 3/4 3/4 10 10 10
0.8 3/4 1.5 3/4 3/4 3/4
V V V mA mA pF
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HT82V26A
Symbol Logic Outputs VOH VOL IOH IOL High Level Output Voltage (SDATA, D0~D7) Low Level Output Voltage (SDATA, D0~D7) High Level Output Current Low Level Output Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 DRVDD-0.5 3/4 3/4 3/4 3/4 3/4 1 1 3/4 0.5 3/4 3/4 V V mA mA Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
A.C. Characteristics
Symbol Power Supplies VADD VDRDD tMAX3 tMAX2 tMAX1 AVDD DRVDD 3-channel Mode with CDS 2-channel Mode with CDS 1-channel Mode with CDS ADC Resolution Integral Nonlinear (INL) Differential Nonlinear (DNL) Offset Error Gain Error Analog Inputs RFS Vi Ci Ii Amplifiers PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution Programmable Offset at Minimum Programmable Offset at Maximum Offset Resolution Temperature Range tA Ptot Operating Total Power Consumption 3/4 3/4 3/4 3/4 0 3/4 3/4 400 70 3/4 C mW Power Consumption 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 5.85 6 -250 250 9 3/4 3/4 3/4 3/4 3/4 3/4 V/V V/V Bits mV mV Bits Full-scale Input Range Input Limits Input Capacitance Input Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 AVSS-0.3 3/4 3/4 2.0 3/4 10 10 3/4 AVDD+0.3 3/4 3/4 Vp-p V pF nA 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4.75 3 30 30 25 3/4 3/4 -1 -100 3/4 5 5 3/4 3/4 3/4 16 32 3/4 3/4 5 5.25 5.25 3/4 3/4 3/4 3/4 3/4 1 100 3/4 V V MSPS MSPS MSPS Bits LSB LSB mV %FSR Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Maximum Conversion Rate
Accuracy (Entire Signal Path)
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HT82V26A
Timing Specification Symbol Clock Parameters tPRA tPRB tPRC tADCLK tC1 tC2 tC1C2 tADC1 tADC2 tAD taC2C1 taC2ADR tbC2ADR tbC1ADR tbC2C1 tcC2C1 tcC1ADF tcC2ADR fSCLK tLS tLH tDS tDH tRDV Data Output tOD Output Delay Latency (Pipeline Delay) 3/4 3/4 8 9 3/4 3/4 ns Cycles 3-channel pixel rate 2-channel (Even-Odd) pixel rate 1-channel pixel rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Rising to CDSCLK1 Falling ADCCLK Rising to CDSCLK2 Falling Analog Sampling Delay CDSCLK2 Falling to CDSCLK1 Rising CDSCLK2 Falling to ADCCLK Rising CDSCLK2 Falling to ADCCLK Rising CDSCLK1 Rising to ADCCLK Rising CDSCLK2 Falling to CDSCLK1 Rising CDSCLK2 Falling to CDSCLK1 Rising CDSCLK1 Rising to ADCCLK Falling CDSCLK2 Falling to CDSCLK1 Rising Maximum SCLK Frequency SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time Falling to SDATA Valid 100 66 40 16 12 12 0 0 0 5 30 30 30 15 15 15 0 20 10 10 10 10 10 10 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns Parameter Min. Typ. Max. Unit
3-Channel Mode Only
2-Channel Mode Only
1-Channel Mode Only
Serial Interface
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Functional Description
Integral Nonlinear (INL) Integral nonlinear error refers to the deviation of each individual code from a line drawn from zero scale through a positive full scale. The point used as zero scale occurs 1/2 LSB before the first code transition. A positive full scale is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinear (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed for the 16-bit resolution indicates that all the 65536 codes respectively, are present in the over-all operating range. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. Internal Register Descriptions Register Name Address A2 0 A1 0 A0 0 D8 0 D7 0 D6 1 D5 3-CH D4 CDS on Data Bits D3 Clamp Voltage Delay enable D2 Enable Power Down D1 Output Delay D0 1 byte out The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value of 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and the last code transitions and the ideal difference between the first and the last code transitions. Aperture Delay The aperture delay is the time delay that occurs when a sampling edge is applied to the HT82V26A until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clocks falling edge to the instant the actual internal sample is taken.
Configuration
MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
0 0 0 0 MSB MSB MSB
RGB/ Red Green Blue BGR 0 0 0 0 0 0 MSB MSB MSB
CDSCLK1 CDSCLK2 ADCCLK delay delay delay LSB LSB LSB LSB LSB LSB
Internal Register Map Configuration Register The configuration register controls the HT82V26As operating mode and bias levels. Bits D6 should always be set high. Bit D5 will configure the HT82V26A for the 3-channel (high) mode of operation. Setting the bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the HT82V26As input clamp. This bit should always be set high for the 4V clamp bias, unless a CCD with a reset feed through transient exceeding 2V is used. Setting the bit D3 low, the clamp voltage is 3V. Bit D2 controls the power-down mode. Setting bit D2 high will place the HT82V26A into a very low power sleep mode. All register contents are retained while the HT82V26A is in the power-down state. Setting bit D1 high will configure the HT82V26A for the digital output (D0~D7) delay 2ns. Bit D0 controls the output mode of the HT82V26A. Setting bit D0 high will enable a single byte output mode where only 8 MSBs of the 16b ADC is output. If bit D0 is set low, then the 16b ADC output is multiplexed into two bytes.
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D8 D7 D6 D5 D4 D3 D2 D1 D0
3 channels CDS operation Clamp bias Power-down Set to 0 Set to 0 Set to 1 1=On* 0=Off 1=CDS mode* 1=4V* 0=SHA mode 0=3V 1=On
1 byte out Output delay (High-byte only) 1=On 1=On 0=Off*
0=Off (Normal)* 0=Off*
Configuration Register Settings Note: * Power-on default value MUX Register The MUX register controls the sampling channel order and the 2-channel mode configuration in the HT82V26A. Bits D8 should always be set low. Bit D7 is used when operating in the 3-channel mode or the 2-channel mode. Setting bit D7 high will sequence the MUX to sample the red channel first, then the green channel, and then the blue channel. When in the 3-channel mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first (see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 rising edge will always reset the MUX to sample the blue channel first. Bits D6, D5 and D4 are used when operating in 1 or 2-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-channel mode. The two channel mode is selected by setting two of the channel select bits (D4~D6) high. The MUX samples the channels in the order selected by bit D7. Bits D0~D3 are used for controlling CDSCLK1, CDSCLK2 and ADCCLK internal delay. D8 D7 MUX Order Set to 0 1=R-G-B* 0=B-G-R D6 D5 Channel Select 1=RED* 1=GREEN 0=Off 0=Off* 1=BLUE 0=Off* D4 D3 0=Off 1=On* D2 0=2ns* 1=4ns D1 0=2ns* 1=4ns D0 0=0ns* 1=2ns
Enable Delay CDS1 Delay
CDS2 Delay ADCK Delay
MUX Register Settings Note: * Power-on default value PGA Gain Registers There are three PGA registers for use in individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See figure for a graph of the PGA gain versus PGA register code. The coding for the PGA registers is a straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x). The HT82V26A uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1x (0dB) to 5.85x (15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in nonlinear proportion with the register 5.85 code, according to the following the equation: Gain= 63 - G 1+ 4.85x( ) 63 Where G is the decimal value of the gain register contents, and varies from 0 to 63.
15 12 5 .8 5 5 .0 9 4 .0 6 3 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 6063 P G A r e g is te r v a lu e - - D e c im a l 3 .0 2 .0 1 .0
)
PGA Gain Transfer Function Rev. 1.00 7 August 16, 2005
G A IN -V /V (
G A IN -d B (
)
HT82V26A
D8 Set to 0 0 0 D7 Set to 0 0 0 D6 Set to 0 0 0 D5 MSB 0 0 0 0 0 0 . . . 1 1 0 0 0 0 D4 D3 D2 D1 D0 LSB 0* 1 1.0 1.013 . . . 5.43 5.85 0.0 0.12 . . . 14.7 15.3 Gain (V/V) Gain (dB)
0 0
0 0
0 0
1 1
1 1
1 1
1 1
0 1
PGA Gain Register Settings Note: * Power-on default value Offset Registers There are three offset registers for use in individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control the offset range from -250mV to 250mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. The Table shows the offset range as a function of the bits D8 through D0. D8 MSB 0 0 0 0 0 0 0 0 0 0 0 0 . . . 1 0 0 . . . 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB 0* 1 0 0.98 . . . 250 0 -0.98 . . . -250 Offset (mV)
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1
1
1
1
1
1
1
1
Note: * Power-on default value
Timing Diagrams
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D8
D7
D6
D5
D4
D3
D2
D1
D0
tL
H
SLO AD
Serial Write Operation Timing
SDATA SC LK
R /W b
A2
A1
A0
D8
tR
D7
DV
D6
D5
D4
D3
D2
D1
D0
tL
S
tL
H
SLO AD
Serial Read Operation Timing
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HT82V26A
A n a lo g In p u t (R , G , B )
P ix e l ( N + 3 ) tA
D
P ix e l ( N + 4 )
P ix e l ( N + 5 )
tC
1
tP
RA
CDSCLK1 tC CDSCLK2 tA
D CLK 1C2
tC
2
ta
C2C1
tA AD CCLK
DC2
ta
C2ADR
tA
DC1
tA
D CLK
tO
D
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 ) B (N -2 )
R (N -1 )
R (N -1 )
G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 )
R (N )
R (N )
G
(N )
G
(N )
B (N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
3-Channel CCD Mode Timing (Select R-G-B Mode)
A n a lo g In p u t (G , B ) tC
1
P ix e l ( N + 3 )
P ix e l ( N + 4 )
P ix e l ( N + 5 )
P ix e l ( N + 6 )
tA
D
tP
RB
CDSCLK1 tC CDSCLK2 tA
D CLK 1C2
tC
2
tb
C2C1
tb
C1ADR
tA AD CCLK
DC2
tA
DC1
tA
D CLK
tO
D
O u tp u t D a ta D7~D0
B (N -4 )
B (N -4 ) G
(N -3 ) G
(N -3 )
B (N -3 )
B (N -3 ) G
(N -2 ) G
(N -2 )
B (N -2 )
B (N -2 )
G
(N -1 ) G
(N -1 ) B (N -1 ) B (N -1 ) G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
2-Channel CCD Mode Timing (Select G-B Mode)
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HT82V26A
P ix e l (N + 5 ) A n a lo g In p u t P ix e l (N + 6 ) tA
D
P ix e l (N + 7 )
P ix e l (N + 8 )
P ix e l (N + 9 )
P ix e l (N + 1 0 )
P ix e l (N + 1 1 )
tC
1
tP
RC
CDSCLK1 tC CDSCLK2 tA
D CLK C2C1
tC
1C2
tC
2
tC AD CCLK
C1ADF
tA
DC2
tA
D CLK
tO
D
O u tp u t D a ta D7~D0
P ix e l (N -7 )
P ix e l (N -6 ) H ig h B y te
P ix e l (N -6 ) Low B y te
P ix e l (N -5 ) H ig h B y te
P ix e l (N -5 ) Low B y te
P ix e l (N -4 ) H ig h B y te
P ix e l (N -4 ) Low B y te
P ix e l (N -3 ) H ig h B y te
P ix e l (N -3 ) Low B y te
P ix e l (N -2 ) H ig h B y te
P ix e l (N -2 ) Low B y te
P ix e l (N -1 ) H ig h B y te
P ix e l (N -1 ) Low B y te
P ix e l (N ) H ig h B y te
P ix e l (N ) Low B y te
P (N H B
ix e l +1) ig h y te
1-Channel CCD Mode Timing
P ix e l ( N + 3 )
A n a lo g In p u t (R , G , B )
P ix e l ( N + 4 )
P ix e l ( N + 5 )
tA
D
tC
2
tP
RA
CDSCLK2 tA
D CLK
tA AD CCLK
DC2
ta
C2ADR
tA
DC2
tO
D
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 ) B (N -2 )
R (N -1 )
R (N -1 )
G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 )
R (N )
R (N )
G
(N )
G
(N )
B (N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
3-Channel SHA Mode Timing (Select R-G-B Mode)
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P ix e l ( N + 5 ) P ix e l ( N + 4 ) tA
D
P ix e l ( N + 3 )
P ix e l ( N + 6 )
A n a lo g In p u t (G , B ) tC
2
tb
C2ADR
tb
PRB
CDSCLK2 tA
D CLK
tA
DC2
tA
DC2
tb
C2ADR
tA
D CLK
AD CCLK tO
D
O u tp u t D a ta D7~D0
B (N -4 )
B (N -4 ) G
(N -3 ) G
(N -3 )
B (N -3 )
B (N -3 ) G
(N -2 ) G
(N -2 )
B (N -2 )
B (N -2 )
G
(N -1 ) G
(N -1 ) B (N -1 ) B (N -1 ) G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
2-Channel SHA Mode Timing (Select G-B Mode)
P ix e l (N + 5 ) A n a lo g In p u t
tA
D
P ix e l (N + 6 )
P ix e l (N + 7 ) P ix e l (N + 8 )
tC
2
P ix e l (N + 1 0 ) P ix e l (N + 9 )
P ix e l (N + 1 1 )
tP
RC
CDSCLK2 tC AD CCLK tO
D
C2ADF
tA
tA D C 2 DC2
tC
C2ADF
tA
D CLK
tA
D CLK
O u tp u t D a ta D7~D0
P ix e l (N -7 )
P ix e l (N -6 ) H ig h B y te
P ix e l (N -6 ) Low B y te
P ix e l (N -5 ) H ig h B y te
P ix e l (N -5 ) Low B y te
P ix e l (N -4 ) H ig h B y te
P ix e l (N -4 ) Low B y te
P ix e l (N -3 ) H ig h B y te
P ix e l (N -3 ) Low B y te
P ix e l (N -2 ) H ig h B y te
P ix e l (N -2 ) Low B y te
P ix e l (N -1 ) H ig h B y te
P ix e l (N -1 ) Low B y te
P ix e l (N ) H ig h B y te
P ix e l (N ) Low B y te
P (N H B
ix e l +1) ig h y te
1-Channel SHA Mode Timing
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HT82V26A
Application Circuits
The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below. The recommended input coupling capacitor value is 0.1mF. A single ground plane is recommended for the HT82V26A. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V26A. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1mF decoupling capacitors should be located as close as possible to the HT82V26A pins. When operating in a single channel mode, the unused analog inputs should be grounded.
V C lo c k In p u ts 1 2 3 5 V /3 V 4 5 6 7 8 9 10 11 12 13 D a ta In p u ts 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F
DD
CDSCLK1 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
0 .1 m F
R e d In p u t G re e n In p u t B lu e In p u t 1 .0 m F
H T82V26A
(C D S M o d e )
V
DD
C lo c k In p u ts 1 2 3 5 V /3 V 4 5 6 7 8 9 10 11 12 13 D a ta In p u ts 14
CDSCLK1 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0 .1 m F
R e d In p u t G re e n In p u t B lu e In p u t DC Level
0 .1 m F
0 .1 m F 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts 0 .1 m F
H T82V26A
(S H A
M ode)
Note:
For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V26A without the use of coupling capacitors. The OFFSET pin should be grounded if the inputs to the HT82V26A are to be referenced to ground, or a DC offset voltage should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs. The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.
Rev. 1.00
12
August 16, 2005
HT82V26A
Package Information
28-pin SSOP (209mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 291 196 9 396 65 3/4 4 26 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25.59 3/4 3/4 3/4 3/4 Max. 323 220 15 407 73 3/4 10 34 8 8
Rev. 1.00
13
August 16, 2005
HT82V26A
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.00
14
August 16, 2005
HT82V26A
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
Rev. 1.00
15
August 16, 2005
HT82V26A
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.00
16
August 16, 2005
HT82V26A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
17
August 16, 2005

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